Since an SRAM (static random access memory) does not require a refresh operation, a power consumption of the SRAM is lower than that of a DRAM (dynamic random access memory), and an operation speed of the SRAM is higher than that of the DRAM. For this reason, the SRAM is widely used for a cache memory of a computer or a mobile electronic appliance. Memory cells used in the SRAM include a high-resistance type cell and a CMOS type cell. The CMOS type cell is configured by six transistors, i.e., one pair of access transistors, one pair of drive transistors, and one pair of load transistors.
A method of relieving read disturbance by configuring an SRAM cell with 10 transistors obtained by adding one pair of read access transistors and one pair of read drive transistors to a CMOS type cell configured by six transistors is known. The relieving method is disclosed in Japanese Patent Application Publication No. 2009-43304.
In the relieving method, a serial buffering N-channel MOS transistor is connected between an access transistor of an SRAM cell and a bit line corresponding to the access transistor, and an intermediate node drive N-channel MOS transistor is connected between a connection node of series transistors and a low-side power supply, for example. The intermediate node drive transistor connects a gate to a storage node which is the same as a corresponding drive transistor. In the relieving method, the SRAM cell is configured by 10 transistors and improves at least a read margin even at a low power supply voltage.
A method in which first and second word lines commonly arranged in a plurality of memory cells, a plurality of power supply lines arranged to correspond to the plurality of memory cells, respectively, a plurality of pairs of first and second bit lines arranged to correspond to the plurality of memory cells, a row decoder which sequentially activates the first word line and the second word line when data is written, and a control circuit which sets a power supply line of a selected memory cell in a floating state when data is written and sets power supply lines of non-selected memory cells to a ground voltage are arranged to configure an SRAM with 10 transistors and to further improve the stability of data retention in a memory cell is also known. The stability improving method is disclosed in Japanese Patent Application Publication No. 2008-293591.
Relief of read disturbance and improvement of stability of data retention are disclosed in I. J. Chang et al., “A 32 kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90 nm CMOS”, ISSCC Dig. Tech. Paper, Feb. 2008, pp. 388 to 389.
However, in the SRAM cell configured by the 10 transistors, source potentials of a read drive transistor must be switched when data is read and when data is written, therefore, a current consumption is disadvantageously increased.
For example, when a current of 40 μA is consumed per SRAM cell, and when 128 SRAM cells are connected to each row, a current of 5 mA flows in a common source line commonly connected to sources of read drive transistors of the SRAM cells in the row direction by one switching operation when data is read. For this reason, a sufficiently thick wire is required to secure reliability to electromigration or to suppress a voltage drop caused by a wiring resistance. When a cell array increases in scale, a cell area disadvantageously increases. Since sources of a large number of read ports are connected to the common source line, a parasitic capacitance increases, a power consumption increases, and an operation speed disadvantageously decreases.